A Guide to Analog Asics by Paul M. Brown Jr.

By Paul M. Brown Jr.

Software particular built-in circuits (ASICs), either analog and electronic, became usual procedure point bulding blocks. ASIC proprietors have tried to supply instruments that they wish will permit quite green IC designers (i.e. platforms engineers) to layout subtle customized built-in circuits. This philosophy has been extra winning in electronic know-how than in analog. considerably extra artwork is concerned with analog layout and much fewer automatic instruments can be found. virtually each analog ASIC seller deals varied semiconductor applied sciences, software units, documentation (usually missing intimately and never delivering the right kind heritage and guidelines), and ranging degrees of engineering help. the result's that many engineers who may perhaps use analog ASICs lack the technical info to take action. they aren't definite while customized analog ICs are least expensive or which seller will most sensible serve their wishes. moreover, many engineers would not have enough analog layout adventure, specially with built-in circuits. Consqeuently, many that may benefit from analog ASIC expertise don't use it whereas others have undesirable stories which may have simply been shunned.

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Their performance is fundamentally limited by the diffusions (and their required spacings) from which they are ere- J c x Figure 3-17 C\ 2 3 4 c c c 2 Lateral pnp geometries. 3 Bipolar Transistors 57 ated. The emitter and collector of the lateral pnp are formed from the npn base, which is not a very rich diffusion. This limits the pnp emitter efficiency. 6 mils), which makes the effective base width very wide, increasing the chance of carrier recombination in the base region. This increases the base cur­ rent for a given collector current, resulting in a relatively low beta.

This is why semicustom prototype turn­ around is so fast. 3 Semiconductor Processing 29 Contact opening Oxide ( S i 0 ) 2 Figure 2-15 Contact etch. The metal mask defines the metal areas that must remain to prop­ erly connect the desired circuit. At this point, the chip is like an unetched PC board with the components already stuffed. A photoresist, masking, and etch process removes the undesired metal, leaving the final circuit connected. Figure 2-17 illustrates how the components fab­ ricated during the process described above might be interconnected.

Typical transistor characteristic curves, as seen on a curve tracer (Figure 3-14) show this as a slope of the curves. The extrapolated x-axis intersection of these curves is referred to as the Early voltage. The tran­ sistor's dynamic output impedance R is expressed as the slope of the V versus I curve. Stated another way, R = V / I . For a typical smallsignal npn transistor, V = 200 V. At a collector current of 1 mA, R = 200 V / l mA = 200 k i l It will be shown later how this output impedance can have a dramatic effect on amplifier gain and current source accuracy.

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